Target architecture - Cortex-A53 - for Siemens SIMATIC IOT2050

This phase requires a specific CPU architecture. In this page, we consider registers and instructions based on Cortex-A53 architecture.

Registers

We support Cortex-A53 registers:

ZKP Register	Cortex-A53 Register	Description
x0		Hardwired zero
x1	ra	Return address
x2	sp	Stack pointer
x3	gp	Global pointer
x4	tp	Thread pointer
x5	t0	Temporary register
x6	t1	Temporary register
x7	t2	Temporary register
x8	s0	Platform register
x9	s1	Platform register
x10	a0	Argument register
x11	a1	Argument register
x12	a2	Temporary register
x13	a3	Temporary register
x14	a4	Temporary register
x15	a5	Temporary register
x16	a6	Temporary register
x17	a7	Temporary register
x18	s2	Saved register
x19	s3	Saved register
x20	s4	Saved register
x21	s5	Saved register
x22	s6	Saved register
x23	s7	Saved register
x24	s8	Saved register
x25	s9	Saved register
x26	s10	Saved register
x27	s11	Saved register
x28	t3	Temporary register
x29	t4	Frame pointer
x30	t5	Return address
x31	t6	Integer register

General Data Processing Instructions:

Set Cortex-A53	Description
ADD / SUB	Adds or subtracts two registers or a register and an immediate value
ADC / SBC	Add or subtract with carry, useful for multi-word arithmetic.
NEG	instruction computes the negation of a value and stores it in a destination register
MUL	Multiply two registers
SDIV / UDIV	Signed/Unsigned integer division
UMULH	It multiplies two 64-bit unsigned integers.
SQADD	Adds two signed integers and clamps the result to the range of the destination type
SQSUB / UQSUB	Subtracts two signed or unsigned integers and clamps the result.
SMULL / UMULL	Multiplies two integers and stores the result in a wider register
AND	Logical AND between two registers or a register and an immediate value.
ORR	Logical OR
EOR	Logical XOR
MVM	performs a bitwise NOT on the contents of a source register or immediate value and writes the result to a destination register
BIC	Bit Clear (logical AND NOT).
BFI	Bitfield Insert.
BFXIL	Bitfield Extract and Insert Low.
CCMP	Compares two values conditionally, based on a flag.
CSEL	Selects a value based on a condition.
B	Branches unconditionally to a target address.
BL	Branches to a target address and stores the return address in the LR (Link Register) for procedure calls.
BR	Branches to the address held in a register.
BLR	Branches to the address in a register and saves the return address in LR.
B.<code>	Branches to a target address based on the condition code flags.
RET	Returns to the address stored in the LR.
CMP	Subtracts two values and updates the flags.
TST	Performs a bitwise AND between two values and updates flags.
CSEL	Selects between two values based on a condition.
CCMP	Compares two values if a specific condition is true.
BR and BLR	Branch or call using a register's address.
SVC	Makes a system call to request an OS service.
WFE and WFI	Power-saving instructions that halt the processor until an event or interrupt occurs.
ERET	Returns from an exception to the interrupted program.
FADD / FSUB	Adds or subtracts floating-point numbers.
FMUL / FDIV	Multiply or divide floating-point values.
FSQRT	Computes the square root.
FRECPE	Reciprocal estimate (approximates 1/x).
FCMP	Compares two floating-point numbers.
FCVT	Converts between floating-point types.
SCVTF / UCVTF	Convert integers to floating-point values.
SHL, LSR, ASR	Logical and arithmetic shifts.
EXT	Extracts bytes and concatenates them.
SQADD	Saturating add.
ABD	Computes the absolute difference between corresponding elements.
SDOT / UDOT	Computes dot product for signed/unsigned integers.
AESE	Performs a single round of AES encryption.
AESD	Performs a single round of AES decryption.
AESMC	Applies the MixColumns transformation for encryption.
AESIMC	Applies the inverse MixColumns transformation for decryption.
SHA1C	SHA-1 hash computation round using a constant.
SHA1M	SHA-1 hash computation round using a message word.
SHA1P	SHA-1 hash computation round using a previous hash value.
SHA256H	Performs one round of the SHA-256 compression function.
SHA256H2	Performs the second part of the SHA-256 compression function.
PMULL	Polynomial multiply of two 64-bit operands, producing a 128-bit result.
PMULL2	Polynomial multiply of the high halves of two vector registers.
MSR	Writes a value to a system register.
MRS	Reads a value from a system register.
SVC	Triggers a software interrupt for an operating system service.
HVC	Triggers a hypervisor call.
SMC	Switches to the secure world for TrustZone operations.
ERET	Returns from an exception or interrupt handler.
DAIF	Disable/Enable Interrupt Flags.
DMB	Ensures data operations are completed before subsequent memory operations.
DSB	Ensures all memory operations complete before continuing.
ISB	Ensures instruction pipeline synchronization.
WFI	Stops execution until an interrupt occurs.
WFE	Stops execution until an event occurs.
YIELD	Hints to the processor that it can switch to another thread or task.
BRK	Triggers a breakpoint exception.
SMC	Secure Monitor Call (switch to Secure World).
BRK	Triggers a software breakpoint exception.
DRPS	Debug return from a Pointer Authentication exception.
LDAXR	Load an exclusive value with acquire semantics.
STXR	Store an exclusive value to memory if the exclusive lock is maintained (32-bit or 64-bit).
STLXR	Store an exclusive value with release semantics.
DXP	Load a pair of exclusive values (for 64-bit operations on adjacent memory).
STXP	Store a pair of exclusive values conditionally.
CBNZ	Conditional branch on zero/non-zero (register).
TBZ/TBNZ	Conditional branch on a specific bit in a register (test bit zero/non-zero).
RET	Return from subroutine.

Reference

[1]. https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf

[2].https://www.espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf